A conventional level shift circuit for converting a low-voltage signal into a high-voltage signal requires a circuit for latching input data in order to fix the input data, and an N-type MOS transistor requires a higher current capability than a P-type MOS transistor because the P-type MOS transistor and the N-type MOS transistor are simultaneously turned on during the switching of input data, so that the N-type MOS transistor has to be large in size. Thus, the level shift circuit has a large area and power consumption increases during the switching.
FIG. 25 shows an example of the conventional level shift circuit.
The level shift circuit is constituted of an inverter INV1 operating at a power supply voltage VDD1 of the circuit on the input side, Pch transistors P1 and P2 operating at a power supply voltage VDD2 of the circuit on the output side, Nch transistors N1 and N2, and two inverters INV2 and INV3.
Input signal Data is connected to the gate of the Nch transistor N1 and the input of the inverter INV1, and the output of the inverter INV1 is connected to the gate of the Nch transistor N2.
The source of the Nch transistor N1 is grounded to GND, the drain of the Nch transistor N1 is connected to the drain of the Pch transistor P1 and the gate of the Pch transistor P2, and the source of the Pch transistor P1 is connected to the power supply voltage VDD2.
The source of the Nch transistor N2 is grounded to GND, the drain of the Nch transistor N2 is connected to the drain of the Pch transistor P2, the gate of the Pch transistor P1, and the input of the inverter INV2. The source of the Pch transistor P2 is connected to the power supply voltage VDD2.
The output of the inverter INV2 is a signal OUT1 obtained by level-shifting input data. The signal OUT1 is connected to the input of the inverter INV3. The output of the inverter INV3 is an inverted signal OUT2 of the signal OUT1.
In this configuration, when the input signal Data is at H level, the transistor N1 is turned on, the voltage of a node V11 decreases, and the transistor P2 is turned on. Since the inverted signal of the input signal Data is connected to the gate of the transistor N2, the transistor N2 is turned off. A node V12 is thus set at H level. Therefore, the signal OUT1 is outputted at L level and the signal OUT2 is outputted at H level.
Conversely, when the input signal Data is at L level, the transistor N2 is turned on, the voltage of a node V12 decreases, and the transistor P1 is turned on. Since the input signal Data is at L level, the transistor N1 is turned off. Thus, the node V11 is set at H level. The signal OUT1 is outputted at H level and the signal OUT2 is outputted at L level.
However, when the input signal Data is at H level, the node V11 is at L level, the node V12 is at H level, the transistor N1 is turned on, the transistor N2 is turned off, the transistor P2 is turned on, and the transistor P1 is turned off. When the input signal Data is changed from H level to L level, the transistor N1 is turned off and the transistor N2 is turned on. Thus, the transistors N2 and P2 are turned on and a through current passes through the transistors N2 and P2. Since the voltage of the node V12 has to be reduced to L level, the transistor N2 has to be increased in size.
Also when the input signal Data is changed from L level to H level, a through current passes through the transistors N1 and P1 and the voltage of the node V11 has to be reduced to L level. Thus, the transistor N1 has to be increased in size.
For this reason, the configuration of the conventional level shift circuit has high power consumption and a large circuit size. See Japanese Patent Laid-Open No. 11-136120.
A liquid crystal display driver requires level shift circuits as many as a number obtained by multiplying the number of outputs by the number of bits. For example, when a liquid crystal display driver has 384 outputs of 8 bits, 3072 level shift circuits are used. In the use of such a number of level shift circuits, power consumption is increased by a through current in the level shift circuits. Each of the level shift circuits has a large device size, resulting in a large circuit area.
It is an object of the present invention to provide a level shift circuit which eliminates a through current in the level shift circuit of CMOS structure and has a smaller circuit area than the conventional art.